Printed Circuit Board Defects

During manufacture packaging distribution and assembly there are always opportunities for defects to occur. Hopefully we all try to minimise the number of scraped boards or at least find them as early in the process as possible to reduce the real cost of scrap.

When examining defective boards scraped by the manufacturer or the assembler it is surprising how many are rejected for purely cosmetic defects. Knowing the time and effort that has gone into each circuits manufacture it is disappointing the level of rejects the industry produces. If you are not familiar with how printed boards are produced a guide to the process stages to produce each printed circuit board is available to down load from my Internet Web Page. This is the first of two columns on process defects which will illustrate examples of defects from both fabrication and assembly. In each case providing possible reasons for the faults occurring.

Weak Knee
(Ref 23.tif)

This defect is seen during assembly of tin lead coated circuit boards or during testing for solderability by the circuit fabricator. During application of tin lead normally by solder levelling the edge of the hole can have a very thin coating of less than 1um. If this is the case the solderability life is very short. During soldering the solder finds it difficult to rise on the plate through hole and cover the knee.
The problem is overcome by correct setting of the solder levelling system and providing a tin lead thickness of 2-5um.

Plating Voids
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Plating voids can be caused by a number of process stages most commonly at electroless copper deposition. If poor coverage is seen prior to copper plating often voids will be present. Often they are difficult to see without destructive testing as they do not have much effect on electrical measurements.
Often they can be caused by poor drilling leaving a rough surface, poor agitation allowing bubbles to form in the hole. They may also be caused by process contamination.

During assembly they will cause outgassing during soldering resulting in pin/blow holes in the solder joints. They do not cause reliability problems but are undesirable.

Resist Misalignment
(Ref 76.tif)

Solder mask overlap or misalignment is often caused by poor design where too little room is left around pads. As a guide all resist apertures should be 0.004-0.006" larger than the pad when using photo imaged resist. When screen printing solder resist 0.012-0.014" may be used.
All imaging processes are mechanical an there will be a tolerance which can be overcome with good design for manufacture design rules. One to one resist to pad design is not recommended.

Tooling Hole Damage
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Tooling holes should be dedicated for a specific process and not used for multiple stages during fabrication. They should not be re used for assembly after use during fabrication as damage may occur and their accurate may be affected.

Delamination
(Ref109.tif)
Delamination is most often seen during a soldering process either solder levelling, wave soldering or reflow. It is generally caused by moisture present in the board expanding during soldering and causing layers of the board to separate.

Dendrite Formation 
(107.tif)
A dendrite is a copper growth forming between to contacts when a voltage is applied to the circuit. It is normally seen during testing of circuits during humidity and voltage exposure.
The dendrite forms by electrolysis due to some form of ionic contamination being present of the surface of the board. It can be caused by plating solution, reflow or levelling fluxes not properly cleaned off the surface of the circuit.

Legend Contamination
(97.tif)
Legend ink contamination on solderable pads is a common problem mostly caused by poor circuit design rules. Ink printing is achieved by screening and is an inaccurate process particularly on large panels. During printing the screen that defines the image stretches hence the inaccuracy. Most design engineers do not leave enough room around features.

Knee Cracks
(36.tif)

Cracking on the knee of the copper through hole plating is very uncommon today. During soldering or the application of solder coating by levelling there is a large thermal expansion of the laminate. The expansion takes place in the Z access and if the copper is not ductile crack can be seen at the knee. The problem is normally related to correct additions to the copper plating vat.

Inner Layer Separation
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Inner layers of a multilayer board can separate during any thermal stress. The separation of the copper inner circuitry is stressed and will separate if the adhesion of the copper through hole plating is not sound. The most common reason for layer separation is poor through hole cleaning prior to metalisation. The cleaning process is normally referred to as de smearing. This type of fault is fairly uncommon in current manufacture and rarely seen in field failures.

The examples of printed board defects are all included on two CD-ROM one interactive and the second a photo album. The interactive CD provides examples of the process defects, their causes and cures. This is the second interactive defect guide on CD ROM produced in the industry the first was covered in Asian Electronics Engineer 1997.

Bob Willis is a process engineering consultant based in England dealing with all aspects of electronic manufacture. For further information  or to obtain a copy of some of the material discussed in this column contact him via his Internet Home Page http://www.bobwillis.co.uk